Evaluating Neutron Induced SEE in SRAM-Based FPGA Protected by Hardware-and Software-Based Fault Tolerant Techniques

This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-based techniques combined with a nonintrusive hardware module. We implemented a MIPS-based soft-core processor in a Virtex5 FPGA and hardened it with software-and hardware-based fault tolerance techniques. First fault injection in the configuration memory bitstream was performed in order to verify the feasibility of the proposed approach, detection rates and diagnosis. Furthermore a neutron radiation experiment was performed at LANSCE. Results demonstrate the possibility of employing more flexible fault tolerant techniques to SRAM-based FPGAs with a high detection rate. Comparisons between bitstream fault injection and radiation test is also presented. © 2013 IEEE.