Effective ADC Linearity Testing

This paper deals with the effectiveness of the Sinewave Histogram Test (SHT) for testing analog to Digital Converters (ADCs). The implementation is discussed, with respect to the adopted procedures and to the choice of relevant parameters. Some of the published approximations currently limiting the characterization of the test performance are removed. Furthermore the statistical efficiency of the SHT is evaluated by comparing the associated estimator variance with the corresponding Cramér-Rao Lower Bound (CRLB), theoretically derived assuming sinewaves corrupted by Gaussian noise. Finally, both simulation and experimental results are presented to validate the proposed approach.