This work presents a customized 110 nm CMOS process on high-resistivity substrate tailored for the production of fully-depleted pixel sensors. Starting from n-type substrates, customized surface implantations have been introduced to enable fast and efficient collection of the charge generated by ionizing particles or radiation. Double-sided processing has been used to define the backside electrode and the termination structures needed to bias the sensors at high voltage. A first run showing the feasibility of 300 μm-thick fully-depleted sensors was completed, and several test devices designed for the assessment of the process were fabricated together with a 24 × 24 pixels array with 50 μm pitch. The main technological challenges and the customization of the process are discussed, and electrical measurements on test devices demonstrating the functionality of the termination structures, the full depletion of the substrate and the fast charge collection are presented.

A 110 nm CMOS process for fully-depleted pixel sensors / Pancheri, L.; Olave, J.; Panati, S.; Rivetti, A.; Cossio, F.; Rolo, M.; Demaria, N.; Giubilato, P.; Pantano, D.; Mattiazzo, S.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - ELETTRONICO. - 14:6(2019), pp. C06016-C06016. [10.1088/1748-0221/14/06/C06016]

A 110 nm CMOS process for fully-depleted pixel sensors

Pancheri L.;
2019

Abstract

This work presents a customized 110 nm CMOS process on high-resistivity substrate tailored for the production of fully-depleted pixel sensors. Starting from n-type substrates, customized surface implantations have been introduced to enable fast and efficient collection of the charge generated by ionizing particles or radiation. Double-sided processing has been used to define the backside electrode and the termination structures needed to bias the sensors at high voltage. A first run showing the feasibility of 300 μm-thick fully-depleted sensors was completed, and several test devices designed for the assessment of the process were fabricated together with a 24 × 24 pixels array with 50 μm pitch. The main technological challenges and the customization of the process are discussed, and electrical measurements on test devices demonstrating the functionality of the termination structures, the full depletion of the substrate and the fast charge collection are presented.
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Pancheri, L.; Olave, J.; Panati, S.; Rivetti, A.; Cossio, F.; Rolo, M.; Demaria, N.; Giubilato, P.; Pantano, D.; Mattiazzo, S.
A 110 nm CMOS process for fully-depleted pixel sensors / Pancheri, L.; Olave, J.; Panati, S.; Rivetti, A.; Cossio, F.; Rolo, M.; Demaria, N.; Giubilato, P.; Pantano, D.; Mattiazzo, S.. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - ELETTRONICO. - 14:6(2019), pp. C06016-C06016. [10.1088/1748-0221/14/06/C06016]
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11572/248812
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