Transmission efficiency of wireless sensor networks (WSN) is lower than that of conventional networks due to frequent propagation errors. In light of specific features and diverse applications of WSN, common assumptions from communication systems may not hold true and efficient application-specific protocols can be formulated. In this paper, we demonstrate this based on an interesting observation related to shortened Reed-Solomon (RS) codes for packet reliability in WSN. We show that multiple instances (gamma) of RS codes defined on a smaller alphabet combined with interleaving result in smaller resource usage while the performance exceeds the benefits of a shortened RS code defined over a larger alphabet. In particular, the proposed scheme can have an error correction capability of up to gamma times larger that for the conventional RS scheme without changing the rate of the code with much lower power, timing and memory requirements. Implementation results on 25 mm motes developed by Tyndall National Institute show that such a scheme is 43% more power efficient compared to RS scheme with same code rate. Besides, such an approach results in 44% faster computations and 53% reduction in memory required.

Low Cost Error Recovery in Delay-Intolerant Wireless Sensor Networks

Sala, Massimiliano;
2007-01-01

Abstract

Transmission efficiency of wireless sensor networks (WSN) is lower than that of conventional networks due to frequent propagation errors. In light of specific features and diverse applications of WSN, common assumptions from communication systems may not hold true and efficient application-specific protocols can be formulated. In this paper, we demonstrate this based on an interesting observation related to shortened Reed-Solomon (RS) codes for packet reliability in WSN. We show that multiple instances (gamma) of RS codes defined on a smaller alphabet combined with interleaving result in smaller resource usage while the performance exceeds the benefits of a shortened RS code defined over a larger alphabet. In particular, the proposed scheme can have an error correction capability of up to gamma times larger that for the conventional RS scheme without changing the rate of the code with much lower power, timing and memory requirements. Implementation results on 25 mm motes developed by Tyndall National Institute show that such a scheme is 43% more power efficient compared to RS scheme with same code rate. Besides, such an approach results in 44% faster computations and 53% reduction in memory required.
2007
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Seville
IEEE
9781424413416
Sala, Massimiliano; R., Agarwal; E., Popovici; B., O'Flynn
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/92285
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