We have identified patterns in the decoding process, which can be exploited to decrease the power consumption of the LDPC sum-product decoder. Results of simulations are produced with the proposed variations for the binary case demonstrating up to 40 % power saving, while suffering a modest performance loss.
Efficient low-density parity-check decoding
Sala, Massimiliano
2004-01-01
Abstract
We have identified patterns in the decoding process, which can be exploited to decrease the power consumption of the LDPC sum-product decoder. Results of simulations are produced with the proposed variations for the binary case demonstrating up to 40 % power saving, while suffering a modest performance loss.File in questo prodotto:
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