We have identified patterns in the decoding process, which can be exploited to decrease the power consumption of the LDPC sum-product decoder. Results of simulations are produced with the proposed variations for the binary case demonstrating up to 40 % power saving, while suffering a modest performance loss.

Efficient low-density parity-check decoding

Sala, Massimiliano
2004-01-01

Abstract

We have identified patterns in the decoding process, which can be exploited to decrease the power consumption of the LDPC sum-product decoder. Results of simulations are produced with the proposed variations for the binary case demonstrating up to 40 % power saving, while suffering a modest performance loss.
2004
The Irish Signal and Systems Conference 2004
Belfast, Northern Ireland
Stevenage : Institution of Electrical Engineers
9780863414404
R. Bresnan: W., Marnane; Sala, Massimiliano
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/89348
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