SDR Implementation of a Low Complexity and Interference-Resilient Space-Time Block Decoder for MIMO-OFDM Systems

In the recent wireless systems, MIMO technologies are largely used to increase data throughput. Many efficient solutions have been proposed for the classical 2 transmitting and 2 receiving antennas (2x2) configuration, such as: the Spatial Multiplexing (SM) and the Alamouti’s Space Time Block Coding (STBC). The extension of these techniques in terms of antennas number is a key topic in MIMO signal processing. In these cases, the computational burden increases due to the large number of elementary operations. Moreover, additional interference due to the non-perfect orthogonality of space-time coding may affect the decoder. In this paper an SDR implementation of a 4x4 STBC configuration for MIMO-OFDM systems is considered. The aim is to introduce a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding. In the literature, feedback techniques have been proposed to solve this problem. However, the algorithm introduced in this paper has been conceived in order to avoid the transmission feedback, by estimating the interference factors and removing them. The related STBC decoder has been implemented on FPGA. The considered algorithm exhibits a low computational complexity and complies with the requirements of HW feasibility, considering the execution time/area occupation trade-off.