A 256x256 SPAD Imager Architecture with Multi-Functional Pixel and High Temporal Aperture for Quantum Imaging Applications

In this paper we describe the architecture of a 256x256 Single Photon Avalanche Diode (SPAD) imager designed for quantum imaging applications in a 110nm CMOS Sensor Imaging process. The chip features a 256x256 SPAD array with 30 mu m pitch and reconfigurable pixel multi-functionality i.e. photon counting with fast gating mode or continuous time stamping of time correlated events with an external trigger. The array is organized in macro-pixels composed of clusters of 2x2 SPADs sharing the Time-to-Digital Converter (TDC), a logic arbiter circuit and other in-pixel circuitry reaching a remarkable. 22% Fill Factor despite the small pixel area. To optimize the usage of the available electronics, we designed an architecture which can share the in-pixel resources also among the neighboring macro-pixels laying on the same line. We split the chip in two independent halves with dedicated readout circuitry to improve the data throughput guaranteeing the possibility to sustain a maximum expected photon rate of 100 Mphotons/s impinging on the focal plane array. To this end, a row and a column zero-suppression logic circuit have been envisaged to save time during the matrix readout phase increasing the chip frame rate.

In this paper we describe the architecture of a 2 5 6 × 2 5 6 Single Photon Avalanche Diode (SPAD) imager designed for quantum imaging applications in a 110 nm CMOS Sensor Imaging process. The chip features a 256 × 256 SPAD array with 30 μm pitch and reconfigurable pixel multi-functionality i.e. photon counting with fast gating mode or continuous time stamping of time correlated events with an external trigger. The array is organized in macro-pixels composed of clusters of 2 × 2 SPADs sharing the Time-to-Digital Converter (TDC), a logic arbiter circuit and other in-pixel circuitry reaching a remarkable ≃ 22% Fill Factor despite the small pixel area. To optimize the usage of the available electronics, we designed an architecture which can share the in-pixel resources also among the neighboring macro-pixels laying on the same line. We split the chip in two independent halves with dedicated readout circuitry to improve the data throughput guaranteeing the possibility to sustain a maximum expected photon rate of 100 Mphotons/s impinging on the focal plane array. To this end, a row and a column zero-suppression logic circuit have been envisaged to save time during the matrix readout phase increasing the chip frame rate.