ARCHYTAS aims to design and evaluate nonconventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.

ARCHYTAS aims to design and evaluate nonconventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project / Agosta, Giovanni; Cherubin, Stefano; Christ, Derek; Conti, Francesco; Djupdal, Asbjørn; Jung, Matthias; Keramidas, Georgios; Passerone, Roberto; Rech, Paolo; Ricci, Elisa; Velha, Philippe; Vella, Flavio; Yildirim, Kasim Sinan; Wilbert, Nils. - (2025), pp. 887-892. ( 28th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025 Kalamata, Greece 06-09 July 2025) [10.1109/isvlsi65124.2025.11130220].

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project

Conti, Francesco;Passerone, Roberto;Rech, Paolo;Ricci, Elisa;Velha, Philippe;Vella, Flavio;Yildirim, Kasim Sinan;
2025-01-01

Abstract

ARCHYTAS aims to design and evaluate nonconventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.
2025
2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
New York, USA
IEEE Computer Society
9798331534776
Agosta, Giovanni; Cherubin, Stefano; Christ, Derek; Conti, Francesco; Djupdal, Asbjørn; Jung, Matthias; Keramidas, Georgios; Passerone, Roberto; Rech,...espandi
Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project / Agosta, Giovanni; Cherubin, Stefano; Christ, Derek; Conti, Francesco; Djupdal, Asbjørn; Jung, Matthias; Keramidas, Georgios; Passerone, Roberto; Rech, Paolo; Ricci, Elisa; Velha, Philippe; Vella, Flavio; Yildirim, Kasim Sinan; Wilbert, Nils. - (2025), pp. 887-892. ( 28th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025 Kalamata, Greece 06-09 July 2025) [10.1109/isvlsi65124.2025.11130220].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/472110
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