This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, lowdamage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature. © 2012 IEEE.
Silicon nanowire devices with widths below 5 nm / Mirza, M. M; Velha, Philippe; Ternent, G.; Zhou, H. P.; Docherty, K. E.; Paul, D. J.. - In: PROCEEDINGS OF THE ... IEEE CONFERENCE ON NANOTECHNOLOGY. - ISSN 1944-9399. - (2012), pp. 1-4. (Intervento presentato al convegno 2012 12th IEEE International Conference on Nanotechnology, NANO 2012 tenutosi a Birmingham, gbr nel 2012) [10.1109/NANO.2012.6322005].
Silicon nanowire devices with widths below 5 nm
VELHA, PHILIPPESecondo
;
2012-01-01
Abstract
This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, lowdamage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature. © 2012 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione
