Selective hardening is a promising solution to efficiently improve the reliability of high performance and safety-critical real-time applications. One of the most significant challenges of selective hardening is to choose how many resources or code portions to protect to avoid unnecessary system performances degradation (at least 2x overhead for the naive duplication). In this paper, we propose a selective hardening strategy for parallel algorithms. We first identify through extensive fault-injection campaigns the code portions whose protection significantly increases the algorithm reliability. Then, we select the code portions that, once protected, maximize the reliability/overhead ratio. We can achieve fault coverage as high as 60% with a 3% overhead. We show that the hardening efficiency can be higher than 90% when compared to naive full duplication.

Increasing the efficiency and efficacy of selective-hardening for parallel applications / Oliveira, D.; Navaux, P.; Rech, P.. - (2019), pp. 1-6. ((Intervento presentato al convegno 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 tenutosi a nld nel 2019 [10.1109/DFT.2019.8875300].

Increasing the efficiency and efficacy of selective-hardening for parallel applications

Rech P.
2019-01-01

Abstract

Selective hardening is a promising solution to efficiently improve the reliability of high performance and safety-critical real-time applications. One of the most significant challenges of selective hardening is to choose how many resources or code portions to protect to avoid unnecessary system performances degradation (at least 2x overhead for the naive duplication). In this paper, we propose a selective hardening strategy for parallel algorithms. We first identify through extensive fault-injection campaigns the code portions whose protection significantly increases the algorithm reliability. Then, we select the code portions that, once protected, maximize the reliability/overhead ratio. We can achieve fault coverage as high as 60% with a 3% overhead. We show that the hardening efficiency can be higher than 90% when compared to naive full duplication.
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
usa
Institute of Electrical and Electronics Engineers Inc.
978-1-7281-2260-1
Oliveira, D.; Navaux, P.; Rech, P.
Increasing the efficiency and efficacy of selective-hardening for parallel applications / Oliveira, D.; Navaux, P.; Rech, P.. - (2019), pp. 1-6. ((Intervento presentato al convegno 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 tenutosi a nld nel 2019 [10.1109/DFT.2019.8875300].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/346711
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