Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module's performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space- and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module's throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces. We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent space-time language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.

Type-directed scheduling of streaming accelerators / Durst, D.; Feldman, M.; Huff, D.; Akeley, D.; Daly, R.; Bernstein, G. L.; Patrignani, M.; Fatahalian, K.; Hanrahan, P.. - (2020), pp. 408-422. (Intervento presentato al convegno 41st ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2020 tenutosi a London, UK nel 15 - 20 June, 2020) [10.1145/3385412.3385983].

Type-directed scheduling of streaming accelerators

Patrignani M.;
2020-01-01

Abstract

Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module's performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space- and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module's throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces. We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent space-time language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.
2020
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
1515 BROADWAY, NEW YORK, NY 10036-9998 USA
Association for Computing Machinery
978-1-4503-7613-6
Durst, D.; Feldman, M.; Huff, D.; Akeley, D.; Daly, R.; Bernstein, G. L.; Patrignani, M.; Fatahalian, K.; Hanrahan, P.
Type-directed scheduling of streaming accelerators / Durst, D.; Feldman, M.; Huff, D.; Akeley, D.; Daly, R.; Bernstein, G. L.; Patrignani, M.; Fatahalian, K.; Hanrahan, P.. - (2020), pp. 408-422. (Intervento presentato al convegno 41st ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2020 tenutosi a London, UK nel 15 - 20 June, 2020) [10.1145/3385412.3385983].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/336569
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