Automatic Design Space Exploration of Redundant Architectures

In this paper, we propose an approach to automatic Design Space Exploration of redundant Embedded System architectures that is heavily based on their reliability assessment. Given a high-level description of the system, we model the deviation from its nominal behavior, and compute the set of all fault configurations, also referred to as cut-sets, in order to extract a reliability function for the architecture under analysis. We use the reliability function, together with the evaluation of other design objectives, to compare different redundant configurations, thus supporting the exploration of the design space.