Simulation-based verification of hardware systems is well-established in industrial practice thanks to the ease-of-use of the approach and to its scalability. However, it notoriously suffers from the lack of exhaustiveness. On the other hand, while pure formal verification techniques provide high confidence in the design correctness, they are very limited in terms of scalability. As an alternative, semi-formal validation techniques are currently under investigation. Semi-formal approaches fulfil the tradeoff between high-coverage results, scalability of the design, and reduced resource requirements. In this work, a semi-formal approach for hardware verification is presented by exploiting constrained random simulation and extended finite state machine (EFSM) traversal through heuristics. The proposed heuristics aim to uniformly, and rapidly, visit the design space, exploiting a NuSMV-based constraint solving technique to efficiently cover corner cases. In this context, a constraint solv...

Semi-Formal Functional Verification by EFSM traversing via NuSMV / Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Roveri, Marco; Soffia, Stefano. - (2010), pp. 58-65. ( 2010 15th IEEE International High Level Design Validation and Test Workshop, HLDVT'10 Anaheim, CA 10-12/06/2010) [10.1109/HLDVT.2010.5496660].

Semi-Formal Functional Verification by EFSM traversing via NuSMV

Marco Roveri;Stefano Soffia
2010-01-01

Abstract

Simulation-based verification of hardware systems is well-established in industrial practice thanks to the ease-of-use of the approach and to its scalability. However, it notoriously suffers from the lack of exhaustiveness. On the other hand, while pure formal verification techniques provide high confidence in the design correctness, they are very limited in terms of scalability. As an alternative, semi-formal validation techniques are currently under investigation. Semi-formal approaches fulfil the tradeoff between high-coverage results, scalability of the design, and reduced resource requirements. In this work, a semi-formal approach for hardware verification is presented by exploiting constrained random simulation and extended finite state machine (EFSM) traversal through heuristics. The proposed heuristics aim to uniformly, and rapidly, visit the design space, exploiting a NuSMV-based constraint solving technique to efficiently cover corner cases. In this context, a constraint solv...
2010
Proceedings of the High Level Design Validation and Test Workshop
Anaheim, CA
IEEE
9781424478057
Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Roveri, Marco; Soffia, Stefano
Semi-Formal Functional Verification by EFSM traversing via NuSMV / Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Roveri, Marco; Soffia, Stefano. - (2010), pp. 58-65. ( 2010 15th IEEE International High Level Design Validation and Test Workshop, HLDVT'10 Anaheim, CA 10-12/06/2010) [10.1109/HLDVT.2010.5496660].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11572/258787
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