Efficient FPGA Implementation of a STBC-OFDM Combiner for an IEEE 802.16 Software Radio Receiver

In this paper, an efficient FPGA implementation of a 4x4 Space-Time Block Coding (STBC) combiner for MIMO-OFDM software radio receivers is considered. The proposed combiner is based on a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding. In the literature, feedback techniques have been proposed to solve this problem. However, the algorithm introduced in this paper has been conceived in order to avoid the transmission feedback, by estimating the interference factors and removing them. The proposed algorithm exhibits a low computational complexity and complies with the requirements of HW feasibility, considering the execution time/area occupation trade-off.