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Mostrati risultati da 1 a 20 di 173
Titolo Anno di pubblicazione Autori Unitn File
A 32-neurons slice for high speed handwriting recognition 1-gen-1997 Passerone, Roberto +
A Dedicated Image Processor Exploiting both Spatial and Instruction-Level Parallelism 1-gen-1997 Passerone, Roberto +
Modeling Reactive Systems in Java 1-gen-1997 Passerone, Roberto +
Design and Implementation of the PAPRICA Parallel Architecture 1-gen-1998 Passerone, Roberto +
Modeling Reactive Systems in Java 1-gen-1998 Passerone, Roberto +
Automatic Synthesis of Interfaces between Incompatible Protocols 1-gen-1998 Passerone, Roberto +
Modeling Reactive Systems in Java 1-gen-1998 Passerone, Roberto +
Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study 1-gen-1998 Passerone, Roberto +
A Highly Parallel SIMD Processor for Morphological and Neural Image Analysis 1-gen-1999 Passerone, Roberto +
Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems 1-gen-2001 Passerone, Roberto +
Using Multiple Levels of Abstractions in Embedded Software Design 1-gen-2001 Passerone, Roberto +
Constraints Specification at Higher Levels of Abstraction 1-gen-2001 Passerone, Roberto +
A High Speed VLSI Architecture for Handwriting Recognition 1-gen-2001 Passerone, Roberto +
Modeling Techniques in Design-by-Refinement Methodologies 1-gen-2002 Passerone, Roberto +
Convertibility Verification and Converter Synthesis: Two Faces of the Same Coin 1-gen-2002 Passerone, Roberto +
Modeling Techniques in Design-by-Refinement Methodologies 1-gen-2002 Passerone, Roberto +
Modeling Techniques in Design-by-Refinement Methodologies 1-gen-2003 Passerone, Roberto +
Conservative approximations for heterogeneous design 1-gen-2004 Passerone, Roberto +
A Formal Approach to System Level Design: Metamodels and Unified Design Environments 1-gen-2005 Passerone, Roberto +
Interchange Formats for Hybrid Systems: Review and Proposal 1-gen-2005 Passerone, Roberto +
Mostrati risultati da 1 a 20 di 173
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